In most digital devices, various integrated circuits in the form of semiconductor chips are soldered onto a printed circuit board. A number of electrical lines are used to route power, ground, and clock signals to each of these semiconductor chips. In addition, a single electrical line, a group of electrical lines, and/or a bus are typically used for the transmission of multiple electrical signals amongst the various semiconductor chips. These electrical lines and buses are known as traces or interconnections. One or more traces are used to electrically connect certain of these semiconductor chips together. Electrical signals put onto a trace by one semiconductor will propagate to the other connected semiconductor chips. By transmitting and receiving data in the form of electrical signals over the traces, the interconnected semiconductor chips can communicate with and route data amongst themselves.
For example, FIG. 1 is a block diagram illustrating a sample prior art microcomputer 100 and corresponding interconnect topology. An address bus 101, data bus 102, and control bus 103 are used to connect microprocessor 104, erasable programmable read only memory (EPROM) 105, random access memory (RAM) 106, and input/output (I/O) chip 107. Microprocessor 104 is the central processing unit for processing data according to a computer program. Computer programs are stored within EPROM 105. Data is stored by RAM 106. I/O chip 107 is used to interface microcomputer 100 with other devices (e.g., keyboard, mouse, a computer display, disk drive, printer, etc.) for inputting and outputting electrical signals. Each chip has a designated address. A particular chip is selected according to the address specified by the electrical signals on address bus 101. Data is routed amongst the chips by data bus 102. Control bus 103 regulates the flow and timing of data to and from the various chips and performs other miscellaneous control functions. Many different types of bus standards have been specified by the Institute of Electrical and Electronics Engineers (IEEE) and other organizations to facilitate the interconnection of processors, memories, and other integrated circuits.
Typically, these traces are configured in a standard open topology (SOT), having the form of a straight line segment. Semiconductor chips are typically coupled to the ends of a trace and at various points along the trace. In order to ensure that the electrical signal, which often takes the form of electrical pulses, has enough power to propagate from one semiconductor chip to any of the other semiconductor chips, drivers are typically utilized. Hence, each chip on the bus typically has a driver for driving signals onto the trace with sufficient power. In addition, each semiconductor chip typically incorporates a receiver for receiving signals transmitted on the trace.
Traces are typically routed in a semi-random fashion. No consideration is given to stub lengths or interconnect symmetry. For high speed digital designs (i.e., 50 Mhz or greater), ignoring the effects of stub lengths and symmetry could detrimentally impact the signal quality. If a semiconductor chip resides in between the two ends of the bus and a signal is driven onto the bus, the voltage of the signal is split and reflected in both directions. For example, an electrical pulse driven from EPROM 105 onto data bus 102 splits in two directions: to the right (i.e., towards I/O chip 107) and to the left (i.e., towards microprocessor 104). When the voltage reaches the two opposite end points, it is reflected back towards the middle of the bus because of the high input impedances of microprocessor 104 and I/O chip 107. Reflections from these stubs can result in signals which oscillate. Unwanted oscillations may result in erroneous data transmission.
Moreover, these oscillations may induce longer communication delays, especially in cases where signals are sent to multiple receivers (i.e., large fanout signals). This directly translates into a slower transmission rate. In the past, semiconductor chips (e.g., microprocessors, memories, I/O buffers, etc.) were relatively slow. The delays attributed to the bus were negligible in comparison to the limitations inherent to the semiconductor chips. But with the rapid advances made in the design, layout, and manufacturing process in the semiconductor field, semiconductor chips are becoming faster. The trend is towards even faster semiconductor chips in the future. It has come to a point now where the delays impaired by reflections in a typical interconnect is constraining the design of large, extremely high-speed multi-conductor networks in very large scale integration (VLSI) semiconductor architectures.
It is known in the prior art that oscillations can be minimized if stub lengths are "balanced". In other words, the placement and the lengths of the stubs should be carefully selected so that the reflections settle rapidly. However, balancing stub lengths requires an inordinate amount of time and effort. Furthermore, balancing stub lengths is a tricky and delicate operation because the procedure is extremely sensitive to small variations in Icad capacitances, interconnection characteristic impedance, and other parameters.
Oscillations can be minimized and possibly eliminated by implementing parallel terminations. For instance, a termination resistor having a resistance equal to the line's characteristic impedance at the receiving end, can be coupled to the power and/or ground line. However, adding a parallel termination dissipates DC power. Moreover, this approach is inappropriate for many complementary metal oxide semiconductor (CMOS) and transistor-transistor logic (TTL) based designs.
Oscillations can also be minimized or completely eliminated by implementing series terminations. In this approach, the resistance of a driver is matched to the characteristic impedance of the interconnection. A series resistor is implemented to compensate for any mismatches. This approach is compatible with most CMOS and TTL designs, but nevertheless, requires that the stub lengths be tuned in order for it to be effective.
Further complicating matters is the fact that the waveform for a signal depends on where its driver is located in reference to the bus. For example, the impedances seen by a particular driver varies, depending on where the driver is located in reference to the other semiconductor chips coupled onto the bus. The impedance seen from the middle of a bus is different from the impedance seen on either side of the bus. The variations in impedances causes variances in the signal waveforms. Hence, the waveform of a signal is different, depending on the location of its driver in reference to the bus.
Therefore, what is needed is an apparatus and method for minimizing reflections and its attendant oscillations. It would be preferable for such an apparatus and method to be easily implemented and to be relatively insensitive to outside parameters. It would also be highly preferable that tuning not be required.